The conversion of color television system (will be termed simply "television system" hereinafter) involves two major items of conversion as follows.
(1) Conversion of the number of lines and the number of fields.
(2) Conversion of the carrier frequency and modulation mode for the color signal.
Among these items, the number of lines and the number of fields are generally converted via a digital signal processing operation using a digital memory or the like, and the color signal is conventionally converted through decoding and encoding via an analog signal processing operation in general.
A conventional apparatus for converting the television system based on the above-mentioned scheme will be explained with reference to FIG. 5.
FIG. 5 is a block diagram of the conventional television system conversion apparatus. In the figure, symbol 1 denotes an input terminal for receiving a television signal to be converted. 2 is a luminance/chrominance signal separation circuit which separates the input television signal into a luminance signal and a chrominance signal. 38 is a chrominance signal decoding circuit (decoder) performing analog signal processing, and it decodes the chrominance signal into two color difference signals U and V. 39 is an analog-to-digital converter (A/D converter) for the colo signal, and it converts the two color difference signals into a digital signal by multiplexing. 40 is a digital memory for the color signal, and it is used to convert the number of lines and the number of fields through the extraction or interpolation process for the digital color difference signals in response to the controlled write clock and read clock. 41 and 42 are digital-to-analog converters (D/A converters) for the color signal, and they convert the two color difference signals, which have been subjected to the line conversion and field conversion, into analog signals. 43 is a chrominance signal encoding circuit (encoder) performing analog signal processing, and it encodes the two analog color difference signals into a chrominance signal. 6, 9 and 12 are respectively an A/D converter, a digital memory and a D/A converter for the luminance signal, and their operations are identical to those elements processing the color signal. 14 is a sync separation circuit which separates the sync signal from the luminance signal. 44 is a write clock generation circuit and 45 is a read clock generation circuit, with both clocks being controlled for the implementation of line conversion and field conversion. 13 is an output buffer circuit which delivers the converted luminance signal and chrominance signal to an output terminal 19.
The operation of the conventional television system conversion apparatus arranged as described above will be explained by taking an example of the case where a television signal of NTSC system received on the input terminal 1 is converted into a television signal of PAL system on the output terminal 19. The chrominance signal of NTSC system separated by the luminance/chrominance signal separation circuit 2 is demodulated with a right-angle 2-phase carrier of 3.58 MHz by the NTSC-based chrominance signal decoder 38 so that it is decoded into two color difference signals U and V of NTSC system. The decoded color difference signals of NTSC system are converted into digital signals by the A/D converter 39, and thereafter stored in the digital memory 40 in response to the write clock provided by the write clock generation circuit 44. Since the write clock is locked to the sync signal of NTSC system provided by the sync separation circuit 14, the two color difference signals of NTSC system are stored in the digital memory 40 such that their line number and field number are coincident with the line address and field address in the address space of the digital memory 40. Namely, 525 line numbers and 60 field numbers correspond to the addresses. The color difference signals are read out in response to the read clock which is locked to the sync signal of PAL system provided by the read clock generation circuit 45, with the number of lines being increased to 625 through the appropriate interpolation and the number of fields being reduced to 50 through the appropriate extraction, and the signals are converted into two color difference signals of PAL system. The two color difference signals of PAL system read out of the digital memory 40 are converted into analog signals by the D/A converters 41 and 42, and thereafter modulated with a right-angle 2-phase alternation carrier of 4.43 MHz by the chrominance signal encoder 43 of PAL system, resulting in a chrominance signal of PAL system.
The luminance signal of NTSC system separated by the luminance/chrominance signal separation circuit 2 is converted into a digital signal by the A/D converter 6 and then stored in the digital memory 9 in response to the write clock which is locked to the sync signal of NTSC system provided by the write clock generation circuit 44, in the same manner as for the color difference signals. The signal is read out in response to the read clock which is locked to the sync signal of PAL system provided by the read clock generation circuit 45, with the number of lines being increased from 525 to 625 through the interpolation and the number of fields being reduced from 60 to 50 through the extraction, and the resulting luminance signal of PAL system is converted into an analog signal by the D/A converter 12. The chrominance signal and luminance signal converted from NTSC system to PAL system through the foregoing process are delivered to the output terminal 19 by way of the output buffer circuit 13. In this manner, a television signal of NTSC system is converted into a television signal of PAL system.
In the reverse case of converting a television signal of PAL system into a television signal of NTSC system, the luminance/chrominance signal separation circuit 2 is of PAL system, the chrominance signal decoder 38 is of PAL system, and the chrominance signal encoder 43 is of NTSC system. In addition, the write clock generation circuit 44 is designed to produce a write clock which is locked to the sync signal of PAL system, and the read clock generation circuit 45 is designed to produce a read clock which is locked to the sync signal of NTSC system.
The foregoing prior art is disclosed in Japanese Patent Publications Nos. 51-33688 and 52-35493, for example.
However, the conventional television system conversion apparatus arranged as described above needs to have a number of chrominance signal decoders 38 and chrominance signal encoders 43 equal to the number of types of television systems of input signals and the number of types of television systems of output signals. Since these circuits are all based on analog signal processing, their circuit scale is very large and they have many adjustment parameters, and as a result their total cost is high and their reliability is low.
On this account, a conceivable variant design is to configure the chrominance signal decoder and chrominance signal encoder to operate as a digital signal processing unit. However, in the conventional television system conversion apparatus shown in FIG. 5, when the chrominance signal decoder 38 based on the digital signal processing is placed in the rear stage of the A/D converter 39 and the chrominance signal encoder 43 performing digital signal processing is placed in the front stage of the D/A converters 41 and 42, these decoders and encoders performing digital signal processing will have a considerably large circuit scale, causing the apparatus to be of significantly increased cost and to be unsuited to home use and the like.